This invention relates to a cache memory arrangement for use between a central processor and a main memory and comprising a cache memory unit and a control circuit therefor.
In general, pipeline control is used to control an information processing system comprising a cache memory arrangement of the type described. In such an information processing system of a pipeline control type, it is preferable to raise a hit ratio of a cache memory unit and to avoid any turbulence or disturbance of the pipeline control.
For this purpose, a memory control system disclosed in U.S. Pat. No. 3,618,041, issued to Hisashi Horikoshi, comprises, as the cache memory unit, an instruction cache memory for memorizing instructions alone and an operand cache memory for memorizing operands alone. In this structure, instruction readout requests and operand readout requests are individually or independently given to the instruction and the operand cache memories, accompanying the instructions and the operands, respectively. Accordingly, no conflicts take place between the instruction and the operand readout requests even when both of the requests are concurrently delivered from a central processor to the cache memory unit.
As will later be described with reference to a few figures of the accompanying drawings, a cache memory unit is sometimes simultaneously supplied with readout requests and storage requests while the pipeline control proceeds. In other words, the readout requests often conflict with the storage requests at the cache memory unit. With the memory control system disclosed in the above-referenced United States Patent, such a conflict is unavoidable. Therefore, the pipeline control is disturbed on occurrence of the conflicts of the readout requests with the storage requests.
In IBM Technical Disclosure Bulletin Vol. 23, No. 1, p.p. 262-263 published on June 1, 1980, a proposal is made by F. T. Blount et al of deferring a store operation by the use of a single register to transfer stored data from the single buffer to the cache memory during an idle time of the cache memory when conflicts occur between readout and storage requests. This proposal is generally effective but becomes ineffective when storage requests consecutively appear from a central processor. In addition, the stored data in the single register may not be rapidly transferred to the cache memory because an idle time seldom appears in such a single cache memory.